Analytical and Numerical Investigation of Noise in Nanoscale Ballistic Field Effect Transistors

The current of ballistic nanoscale MOSFETs is expected to exhibit shot noise, essentially because the electron distribution is very far from equilibrium. Here, we derive an analytical expression of shot noise in fully ballistic MOSFETs and show how it can be computed on the basis of numerical simulations of the DC electrical properties. We show that the power spectral density of shot noise of the drain current is strongly suppressed as an effect of both Pauli exclusion and electrostatic interaction. The amount of such suppression depends on the device structure, and in particular on the gate capacitance. Results on shot noise of the gate current are also shown, since such the leakage current might be significant in nanoscale MOSFETs, for small equivalent oxide thickness.     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

Input-Free V TP and - V TN Extractor Circuits Realized on the Same Chip

The paper describes a self-biased CMOS transistor circuit with two outputs providing the transistor threshold voltages, V _TP and -V _TN . Both outputs are referenced to the same V _DD supply line, and hence, the circuit can be used as a convenient test device. The V _TP extractor is based on the nested connection of two transistors; the -V _TN extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The circuit was realized in 0.8 m technology, and the results of simulation and experiment are compared. Recommendations to improve the design are given.     

On the Electrostatics of Double-Gate and Cylindrical Nanowire MOSFETs

In this work we investigate and compare the electrostatics of fully-depleted double-gate (dg) and cylindrical nanowire (cnw) mosfets accounting for quantum effects and, in doing so, we propose a new approach for the self-consistent solution of the Schrödinger-Poisson equations based on a rigorous time-independent perturbation method. This study leads to the conclusion that the cylindrical geometry is superior to the equivalent double-gate structure both in terms of the current ratio I_on/I_off and the available voltage gain g_m/g_o, indicating that both the subthreshold slope and the drain-induced barrier lowering (dibl) are better controlled by the cnw-mosfet.     

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes,MOSFETs, and Tunnel FETs for Reconfigurable Computing

In this paper, electrostatically configurable 2D tungsten diselenide (WSe₂) electronic devices are demonstrated. Utilizing a novel triple‐gate design, a WSe₂ device is able to operate as a tunneling field‐effect transistor (TFET), a metal–oxide–semiconductor field‐effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band‐to‐band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self‐consistent full‐band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub‐60 mV dec^?1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low‐power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.     

基于预建模单元的宽带毫米波CMOS晶体管可变栅宽高效建模

Thisworkpresentsahighlyefficientapproachforbroadbandmodelingofmillimeter-waveCMOSFETs with gate width scalability by using pre-modeled cells. Only a few devices with varied gate width are required to be measured and modeled with fixed models, and later used as pre-modeled cells. Then a target device with the desired gate width is constructed by choosing appropriate cells and connecting them with a wiring network. The corresponding scalable model is constructed by incorporating the fixed models of the cells used in the target device and the scalable model of the connection wires. The proposed approach is validated by experiments on 65-nm CMOS process up to 40 GHz and across a wide range of gate widths.     

An analytical compact model for Schottky-barrier double gate MOSFETs

An analytical and explicit compact model for undoped symmetrical silicon double gate MOSFETs (DGMOSFETs) with Schottky barrier (SB) source and drain is presented. The SB MOSFET can be studied as a traditional MOSFET where the doped source/drain regions have been replaced by a metal contact. Due to particular features of this new structure, the main transport mechanisms of these devices differ from those found in traditional MOSFETs. The model developed in this paper is based on a previously published DGMOSFET model which has been extended to include the characteristic tunneling transport mechanisms of SB MOSFET.The proposed model reproduces the well known ambipolar behavior found in SB MOSFET for a wide range of metal source and drain contacts specified through different values of their work function. The model has been validated with numerical data obtained by means of the 2D ATLAS simulator, where a SB DGMOSFET structure has been defined and characterized in order to obtain the transfer and output characteristics for several bias configurations. Devices with two channel lengths (2 μm and 3 μm) has been simulated and modeled.     

Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, G_mmax, and analog figures of merit, such as transconductance over drain current ratio, G_m/I_D, output conductance, G_D, Early voltage, V_EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher G_mmax. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model.     

Carrier Modulation in 2D Transistors by Inserting Interfacial Dielectric Layer for Area-Efficient Computation

2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe₂) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe₂ FETs has been switched from hole to electron. The ultrathin body of WSe₂, combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.